Implementation of Quantized Convolutional Neural Networks using FPGAs

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Recently, FPGAs (field programmable gate arrays) have been widely used in AI applications such as convolutional neural networks (CNNs) that require high-speed computation and low power consumption.This paper introduces a method for implementing LeNet-5, a representative convolutional neural network, on an FPGA.Since FPGAs have limited internal resources, it is necessary to lighten LeNet-5 to ensure highspeed operation and low power consumption.In this paper, we build a LeNet-5 model quantized with 2-bit weights and biases and 2-or 4-bit nodes, and train it using QKeras, which is widely used to train quantized deep learning neural networks.After training, we implement LeNet-5 in VHDL (VHSIC hardware description language) and synthesize it using Vivado.This paper introduces a method to improve operating speed by using ternary weights and biases with values of (-1, 0, 1) to replace multiplication in convolution operations with addition and subtraction operations.In addition, we introduce a method for implementing the rounding and clipping used in the QKeras quantization process on an FPGA.By implementing the proposed method on an FPGA and comparing it with existing methods in terms of operating speed, FPGA resource usage, accuracy, and power consumption, this paper demonstrates that the proposed method is superior in operating speed.